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19-3685; Rev 1; 6/09
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
General Description
The MAX7032 crystal-based, fractional-N transceiver is designed to transmit and receive ASK/OOK or FSK data in the 300MHz to 450MHz frequency range with data rates up to 33kbps (Manchester encoded) or 66kbps (NRZ encoded). This device generates a typical output power of +10dBm into a 50 load, and exhibits typical sensitivities of -114dBm for ASK data and -110dBm for FSK data. The MAX7032 features separate transmit and receive pins (PAOUT and LNAIN) and provides an internal RF switch that can be used to connect the transmit and receive pins to a common antenna. The MAX7032 transmit frequency is generated by a 16bit, fractional-N, phase-locked loop (PLL), while the receiver's local oscillator (LO) is generated by an integer-N PLL. This hybrid architecture eliminates the need for separate transmit and receive crystal reference oscillators because the fractional-N PLL allows the transmit frequency to be set within 2kHz of the receive frequency. The 12-bit resolution of the fractional-N PLL allows frequency multiplication of the crystal frequency in steps of fXTAL / 4096. Retaining the fixed-N PLL for the receiver avoids the higher current drain requirements of a fractional-N PLL and keeps the receiver current drain as low as possible. The fractional-N architecture of the MAX7032 transmit PLL allows the transmit FSK signal to be programmed for exact frequency deviations, and completely eliminates the problems associated with oscillator-pulling FSK signal generation. All frequency-generation components are integrated on-chip, and only a crystal, a 10.7MHz IF filter, and a few discrete components are required to implement a complete antenna/digital data solution. The MAX7032 is available in a small 5mm x 5mm, 32-pin, thin QFN package, and is specified to operate in the automotive -40C to +125C temperature range.
Features
+2.1V to +3.6V or +4.5V to +5.5V Single-Supply Operation Single Crystal Transceiver User-Adjustable 300MHz to 450MHz Carrier Frequency ASK/OOK and FSK Modulation User-Adjustable FSK Frequency Deviation Through Fractional-N PLL Register Agile Transmitter Frequency Synthesizer with fXTAL / 4096 Carrier-Frequency Spacing +10dBm Output Power into 50 Load Integrated TX/RX Switch Integrated Transmit and Receive PLL, VCO, and Loop Filter > 45dB Image Rejection Typical RF Sensitivity* ASK: -114dBm FSK: -110dBm Selectable IF Bandwidth with External Filter RSSI Output with High Dynamic Range Autopolling Low-Power Management < 12.5mA Transmit-Mode Current < 6.7mA Receive-Mode Current < 23.5A Polling-Mode Current < 800nA Shutdown Current Fast-On Startup Feature, < 250s Small 32-Pin, Thin QFN Package
*0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW, average RF power
MAX7032
Applications
2-Way Remote Keyless Entry Security Systems Home Automation Remote Controls Remote Sensing Smoke Alarms Garage Door Openers Local Telemetry Systems
Ordering Information
PART MAX7032ATJ TEMP RANGE -40C to +125C PIN-PACKAGE 32 Thin QFN-EP**
**EP = Exposed pad.
Pin Configuration, Typical Application Circuit, and Functional Diagram appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
ABSOLUTE MAXIMUM RATINGS
HVIN to GND..........................................................-0.3V to +6.0V PAVDD, AVDD, DVDD to GND ................................-0.3V to +4.0V ENABLE, T/R, DATA, CS, DIO, SCLK, CLKOUT to GND ......................................................-0.3V to (HVIN + 0.3V) All Other Pins to GND ...............................-0.3V to (_VDD + 0.3V) Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (derate 21.3mW/C above +70C)....1702mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = PAVDD = HVIN = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at AVDD = DVDD = PAVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage (3V Mode) Supply Voltage (5V Mode) SYMBOL VDD HVIN CONDITIONS HVIN, PAVDD, AVDD, and DVDD connected to power supply PAVDD, AVDD, and DVDD unconnected from HVIN, but connected together Transmit mode, PA off, VDATA at 0% duty cycle (ASK) (Note 2) Transmit mode, VDATA at 50% duty cycle (ASK) (Notes 3, 4) Transmit mode, VDATA at 100% duty cycle (FSK) fRF = 315MHz fRF = 434MHz fRF = 315MHz fRF = 434MHz fRF = 315MHz (Note 4) fRF = 434MHz (Note 2) Receiver (ASK 315MHz) Receiver (ASK 434MHz) Receiver (FSK 315MHz) Supply Current IDD TA < +85C, typ at +25C (Note 4) Receiver (FSK 434MHz) DRX (3V mode) DRX (5V mode) Deep-sleep (3V mode) Deep-sleep (5V mode) Receiver (ASK 315MHz) Receiver (ASK 434MHz) Receiver (FSK 315MHz) TA < +125C typ at +125C (Note 2) Receiver (FSK 434MHz) DRX (3V mode) DRX (5V mode) Deep-sleep (3V mode) Deep-sleep (5V mode) Voltage Regulator VREG HVIN = 5V, ILOAD = 15mA MIN 2.1 4.5 TYP 2.7 5.0 3.5 4.3 7.6 8.4 11.6 12.4 6.1 6.4 6.4 6.7 23.4 67.2 0.8 2.4 6.4 6.7 6.8 7.0 33.5 82.3 8.0 14.9 3.0 MAX 3.6 5.5 5.4 6.7 12.3 mA 13.6 19.1 20.4 7.9 8.3 8.4 8.7 77.3 94.4 8.8 10.9 8.2 8.4 8.7 8.8 103.0 116.1 34.2 39.3 V A mA A mA UNITS V V
2
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = PAVDD = HVIN = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at AVDD = DVDD = PAVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER DIGITAL I/O Input High Threshold Input Low Threshold Pulldown Sink Current Pullup Source Current Output-Low Voltage Output-High Voltage VOL VOH VIH VIL (Note 2) (Note 2) SCLK, ENABLE, T/R, DATA (HVIN = 5.5V) DIO, CS (HVIN = 5.5V) ISINK = 500A ISOURCE = 500A 0.9 x HVIN 0.1 x HVIN 20 20 0.15 HVIN 0.26 V V A A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX7032
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = PAVDD = HVIN = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER GENERAL CHARACTERISTICS Frequency Range Maximum Input Level Transmit Efficiency 100% Duty Cycle Transmit Efficiency 50% Duty Cycle PRFIN fRF = 315MHz (Note 6) fRF = 434MHz (Note 6) fRF = 315MHz (Note 6) fRF = 434MHz (Note 6) ENABLE or T/R transition low to high, transmitter frequency settled to within 50kHz of the desired carrier ENABLE or T/R transition low to high, transmitter frequency settled to within 5kHz of the desired carrier ENABLE transition low to high, or T/R transition high to low receiver startup time (Note 5) RECEIVER 0.2% BER, 4kbps Manchester data rate, 280kHz IF BW, 50kHz FSK deviation, average power (Note 8) ASK (315MHz) ASK (434MHz) FSK (315MHz) FSK (434MHz) -114 -113 -110 -107 46 dB dBm 300 0 32 30 24 22 200 450 MHz dBm % % SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-On Time
tON
350
s
250
Sensitivity
Image Rejection
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3
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = PAVDD = HVIN = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER POWER AMPLIFIER TA = +25C (Note 4) Output Power POUT TA = +125C, AVDD = DVDD = HVIN = PAVDD = +2.1V (Note 2) TA = -40C, AVDD = DVDD = HVIN = PAVDD = +3.6V (Note 4) Modulation Depth Maximum Carrier Harmonics Reference Spur PHASE-LOCKED LOOP Transmit VCO Gain Transmit PLL Phase Noise Receive VCO Gain Receive PLL Phase Noise Loop Bandwidth Minimum Transmit Frequency Step Reference Frequency Input Level Programmable Divider Range LOW-NOISE AMPLIFIER/MIXER (Note 9) LNA Input Impedance ZINLNA Normalized to 50 High-gain state Voltage-Conversion Gain Low-gain state Input-Referred 3rd-Order Intercept Point Mixer Output Impedance LO Signal Feedthrough to Antenna RSSI Input Impedance Operating Frequency 3dB Bandwidth fIF 330 10.7 10 MHz MHz IIP3 High-gain state Low-gain state fRF = 315MHz fRF = 434MHz fRF = 315MHz fRF = 434MHz fRF = 315MHz fRF = 434MHz 1 - j4.7 1 - j3.3 50 45 13 9 -42 -6 330 -100 dBm dBm dB In transmit mode (Note 4) 20 10kHz offset, 500kHz loop BW 1MHz offset, 500kHz loop BW Transmit PLL Receive PLL KVCO 10kHz offset, 200kHz loop BW 1MHz offset, 200kHz loop BW 340 -68 -98 340 -80 -90 200 500 fXTAL / 4096 0.5 27 MHz/V dBc/Hz MHz/V dBc/Hz kHz kHz VP-P With output-matching network 4.6 3.9 10.0 6.7 13.1 82 -40 -50 15.8 dB dBc dBc 15.5 dBm SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = PAVDD = HVIN = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Gain FSK DEMODULATOR Conversion Gain ANALOG BASEBAND Maximum Data Filter Bandwidth Maximum Data Slicer Bandwidth Maximum Peak Detector Bandwidth Maximum Data Rate CRYSTAL OSCILLATOR Crystal Frequency Maximum Crystal Inductance Frequency Pulling by VDD Crystal Load Capacitance Minimum SCLK Setup to Falling Edge of CS Minimum CS Falling Edge to SCLK Rising-Edge Setup Time Minimum CS Idle Time Minimum CS Period Maximum SCLK Falling Edge to Data Valid Delay Minimum Data Valid to SCLK Rising-Edge Setup Time Minimum Data Valid to SCLK Rising-Edge Hold Time Minimum SCLK High Pulse Width Minimum SCLK Low Pulse Width Minimum CS Rising Edge to SCLK Rising-Edge Hold Time Maximum CS Falling Edge to Output Enable Time Maximum CS Rising Edge to Output Disable Time (Note 7) SERIAL INTERFACE TIMING CHARACTERISTICS (see Figure 7) tSC tCSS tCSI tCS tDO tDS tDH tCH tCL tCSH tDV tTR 30 30 125 2.125 80 30 30 100 100 30 25 25 ns ns ns s ns ns ns ns ns ns ns ns fXTAL (fRF - 10.7) / 24 50 2 4.5 MHz mH ppm/V pF Manchester coded NRZ 50 100 50 33 66 kHz kHz kHz kbps 2.0 mV/kHz SYMBOL CONDITIONS MIN TYP 15 MAX UNITS mV/dB
MAX7032
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5
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50 system impedance, AVDD = DVDD = PAVDD = HVIN = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at PAVDD = AVDD = DVDD = HVIN = +2.7V, TA = +25C, unless otherwise noted.) (Note 1) Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match. 100% tested at TA = +125C. Guaranteed by design and characterization overtemperature. 50% duty cycle at 10kHz ASK data (Manchester coded). Guaranteed by design and characterization. Not production tested. Time for final signal detection; does not include baseband filter settling. Efficiency = POUT / (VDD x IDD). Dependent on PC board trace capacitance. The oscillator register (0x05) is set to the nearest integer result of fXTAL / 100kHz (see the Oscillator Frequency Register section). Note 9: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degeneration from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA source to ground. The equivalent input circuit is approximately 50 in series with ~ 2.2pF. The voltage conversion is measured with the LNA input matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the IF filter insertion loss. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Typical Operating Characteristics
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, TA = +25C, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2% average RF power, unless otherwise noted.)
RECEIVER
SUPPLY CURRENT vs. SUPPLY VOLTAGE (ASK MODE)
MAX7032 toc01
SUPPLY CURRENT vs. RF FREQUENCY (ASK MODE)
MAX7032 toc02a
SUPPLY CURRENT vs. RF FREQUENCY (FSK MODE)
TA = +125C
MAX7032 toc02b
7.0 6.8 SUPPLY CURRENT (mA) 6.6 6.4 6.2 6.0 TA = -40C 5.8 5.6 2.1 2.4 2.7 3.0 3.3 TA = +25C TA = +85C TA = +125C
6.8 6.7 SUPPLY CURRENT (mA) 6.6 6.5 TA = +85C 6.4 6.3 6.2 6.1 6.0 300 325 350 375 TA = -40C TA = +25C TA = +125C
7.0 6.9 SUPPLY CURRENT (mA) 6.8 6.7 TA = +25C 6.6 6.5 6.4 TA = -40C TA = +85C
3.6
400
425
450
300
325
350
375
400
425
450
SUPPLY VOLTAGE (V)
RF FREQUENCY (MHz)
RF FREQUENCY (MHz)
6
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, TA = +25C, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2% average RF power, unless otherwise noted.)
MAX7032
RECEIVER
DEEP-SLEEP CURRENT vs. TEMPERATURE
MAX7032 toc03
BIT-ERROR RATE vs. AVERAGE INPUT POWER (ASK DATA)
MAX7030 toc04
BIT-ERROR RATE vs. AVERAGE INPUT POWER (FSK DATA)
MAX7032 toc05
18 16 DEEP-SLEEP CURRENT (A) 14 12 10 8 6 4 2 0 -40 -15 -10 35 60 85 110 TEMPERATURE (C) VCC = +3.6V VCC = +3.0V VCC = +2.1V
100
100
BIT-ERROR RATE (%)
fRF = 434MHz 1 0.2% BER 0.1 fRF = 315MHz 0.01 -121 -119 -117 -115 -113 -111 AVERAGE INPUT POWER (dBm)
BIT-ERROR RATE (%)
10
10 fRF = 434MHz 1 0.2% BER 0.1 fRF = 315MHz 0.01 -116 -114 -112 -110 -108 -106 -104 AVERAGE INPUT POWER (dBm)
SENSITIVITY vs. TEMPERATURE (ASK DATA)
MAX7032 toc06
SENSITIVITY vs. TEMPERATURE (FSK DATA)
MAX7032 toc07
SENSITIVITY vs. FREQUENCY DEVIATION (FSK DATA)
MAX7032 toc08
-102 -105 SENSITIVITY (dBm) -108 -111 -114 -117 -120 -40 -15 10 35 60 85 110 TEMPERATURE (C) fRF = 315MHz fRF = 434MHz
-100 -102 SENSITIVITY (dBm) -104 -106 -108 -110 fRF = 315MHz -112 -40 -15 10 35 60 85 110 TEMPERATURE (C) fRF = 434MHz
-94 -96 SENSITIVITY (dBm) -98 -100 -102 -104 -106 -108 1 10 FREQUENCY DEVIATION (kHz)
100
RSSI vs. RF INPUT POWER
1.6 1.4 1.2 RSSI (V) 1.0 0.8 0.6 0.4 0.2 AGC HYSTERESIS: 3dB 0 -130 -110 -90 -70 -50 -30 -10 10 RF INPUT POWER (dBm) 0 AGC SWITCH POINT LOW-GAIN MODE HIGH-GAIN MODE RSSI (V)
MAX7032 toc09
RSSI AND DELTA vs. IF INPUT POWER
2.1 1.8 1.5 1.2 0.9 0.6 0.3 DELTA RSSI
MAX7032 toc10
1.8
3.5 2.5 1.5 0.5 -0.5 -1.5 -2.5 -3.5 DELTA (%)
-90
-70
-50
-30
-10
10
IF INPUT POWER (dBm)
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7
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, TA = +25C, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2% average RF power, unless otherwise noted.)
RECEIVER
FSK DEMODULATOR OUTPUT vs. IF FREQUENCY
MAX7032 toc11
SYSTEM GAIN vs. IF FREQUENCY
MAX7032 toc12
IMAGE REJECTION vs. TEMPERATURE
fRF = 434MHz
MAX7032 toc13
1.6 FSK DEMODULATOR OUTPUT (V)
50 40 SYSTEM GAIN (dBm) 30 20 10 0 -10 LOWER SIDEBAND 48dB IMAGE REJECTION FROM RFIN TO MIXOUT fRF = 434MHz UPPER SIDEBAND
48
IMAGE REJECTION (dB)
1.2
46
fRF = 315MHz
0.8
44
0.4
0 10.4 10.5 10.6 10.7 10.8 10.9 11.0 IF FREQUENCY (MHz)
-20 0 5 10 15 20 25 30 IF FREQUENCY (MHz)
42 -40 -15 10 35 60 85 110 TEMPERATURE (C)
NORMALIZED IF GAIN vs. IF FREQUENCY
MAX7032 toc14
S11 vs. RF FREQUENCY
MAX7032 toc15
S11 SMITH PLOT OF RFIN
MAX7032 toc16
0
0
NORMALIZED IF GAIN (dB)
-4
-6 S11 (dB) 434MHz -12 433.92MHz
-8
-12 -18
-16
400MHz
500MHz
-20 1 10 IF FREQUENCY (MHz) 100
-24 200 250 300 350 400 450 500 RF FREQUENCY (MHz)
INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION
90 fRF = 315MHz 80 REAL IMPEDANCE () 70 60 50 40 30 20 1 10 INDUCTIVE DEGENERATION (nH) 100 REAL IMPEDANCE IMAGINARY IMPEDANCE -230 IMAGINARY IMPEDANCE () REAL IMPEDANCE () -240 -250 -260 -270 -280 -290 80 70 60 50 40 30 20 1
MAX7032 toc17
INPUT IMPEDANCE vs. INDUCTIVE DEGENERATION
-220 90
MAX7032 toc18
fRF = 434MHz
-150 -160
IMAGINARY IMPEDANCE
-170 -180 -190 -200
REAL IMPEDANCE
-210 -220
10 INDUCTIVE DEGENERATION (nH)
100
8
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IMAGINARY IMPEDANCE ()
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, TA = +25C, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2% average RF power, unless otherwise noted.)
MAX7032
RECEIVER
PHASE NOISE vs. OFFSET FREQUENCY
MAX7032 toc19
PHASE NOISE vs. OFFSET FREQUENCY
fRF = 434MHz
MAX7032 toc20
-50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120 100 1k 10k 100k
fRF = 315MHz
-50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120
1M
10M
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
TRANSMITTER
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7032 toc21
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7032 toc22
SUPPLY CURRENT vs. SUPPLY VOLTAGE
fRF = 434MHz PA ON WITHOUT ENVELOPE SHAPING TA = +85C 13 TA = +125C TA = -40C
MAX7032 toc23
16
fRF = 315MHz PA ON WITHOUT ENVELOPE SHAPING TA = +85C
6.0 5.5 SUPPLY CURRENT (mA) 5.0
fRF = 315MHz PA OFF
17
SUPPLY CURRENT (mA)
TA = +125C 4.5 4.0 3.5 3.0 2.5 TA = +25C TA = -40C TA = +85C
12
TA = +125C TA = -40C
10
TA = +25C
SUPPLY CURRENT (mA)
14
15
11
TA = +25C
8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
2.0 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
9 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7032 toc24
SUPPLY CURRENT vs. OUTPUT POWER
MAX7032 toc25
SUPPLY CURRENT vs. OUTPUT POWER
13 SUPPLY CURRENT (mA) 12 11 10 9 8 7 PA ON fRF = 434MHz ENVELOPE SHAPING ENABLED
MAX7032 toc26
6.0 5.5 SUPPLY CURRENT (mA) 5.0 4.5 4.0 3.5 3.0 2.1
fRF = 434MHz PA OFF TA = +125C TA = +85C
12 11 SUPPLY CURRENT (mA) 10 9 8 7 6
fRF = 315MHz ENVELOPE SHAPING ENABLED
14
PA ON
TA = +25C TA = -40C
5 4 3.3 3.6 -14 -10 -6 -2
50% DUTY CYCLE 2 6 10
6 5 -14 -10 -6 -2
50% DUTY CYCLE 2 6 10
2.4
2.7
3.0
SUPPLY VOLTAGE (V)
AVERAGE OUTPUT POWER (dBm)
AVERAGE OUTPUT POWER (dBm)
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9
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, TA = +25C, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2% average RF power, unless otherwise noted.)
TRANSMITTER
SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR
18 16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0.1 fRF = 315MHz PA ON 1 10 100 1k 10k CURRENT POWER
MAX7032 toc27-1
SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR
16 12 SUPPLY CURRENT (mA) OUTPUT POWER (dBm) 8 4 0 -4 -8 -12 -16 18 16 14 12 10 8 6 4 2 0.1 fRF = 434MHz PA ON 1 10 100 1k 10k CURENT POWER
MAX7032 toc27-2
16 12 OUTPUT POWER (dBm) 8 4 0 -4 -8 -12 -16
EXTERNAL RESISTOR ()
EXTERNAL RESISTOR ()
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7032 28-1
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7032 28-2
OUTPUT POWER vs. SUPPLY VOLTAGE
fRF = 434MHz PA ON ENVELOPE SHAPING DISABLED TA = -40C TA = +25C
MAX7032 29-1
14
12 OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
TA = +25C 10
TA = +25C 10
OUTPUT POWER (dBm)
fRF = 315MHz PA ON ENVELOPE SHAPING DISABLED TA = -40C
14
12
fRF = 315MHz PA ON ENVELOPE SHAPING ENABLED TA = -40C
14
12
10
8 TA = +125C 6 TA = +85C
8 TA = +125C 6 TA = +85C
8 TA = +125C 6 TA = +85C
4 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
4 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
4 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX7032 29-2
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7032 toc30
EFFICIENCY vs. SUPPLY VOLTAGE
fRF = 434MHz PA ON
MAX7032 toc31
14
fRF = 434MHz PA ON ENVELOPE SHAPING ENABLED TA = -40C TA = +25C
40
fRF = 315MHz PA ON
40
TA = -40C
TA = -40C
OUTPUT POWER (dBm)
12 EFFICIENCY (%)
35
TA = +25C EFFICIENCY (%) TA = +85C
35 TA = +25C 30 TA = +85C
10
30
8
TA = +125C TA = +85C
25
25 TA = +125C 20 2.1 2.4 2.7 3.0 3.3 3.6 2.1 2.4 2.7 3.0
TA = +125C
6 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
20 SUPPLY VOLTAGE (V)
3.3
3.6
SUPPLY VOLTAGE (V)
10
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAVDD = AVDD = DVDD = HVIN = +3.0V, fRF = 433.92MHz, TA = +25C, IF BW = 280kHz, data rate = 4kbps Manchester encoded, frequency deviation = 50kHz, BER = 0.2% average RF power, unless otherwise noted.)
MAX7032
TRANSMITTER
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7032 toc32
EFFICIENCY vs. SUPPLY VOLTAGE
MAX7032 toc33
PHASE NOISE vs. OFFSET FREQUENCY
-50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120 -130 -140 3.6 100 1k 10k 100k 1M 10M fRF = 315MHz
MAX7032 toc34
30
fRF = 315MHz 50% DUTY CYCLE TA = -40C TA = +25C
30
fRF = 434MHz 50% DUTY CYCLE
-40
TA = -40C
25 EFFICIENCY (%)
EFFICIENCY (%)
25
TA = +25C
20 TA = +125C 15 TA = +85C
20 TA = +85C TA = +125C
10 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
15 2.1 2.4 2.7 3.0 3.3 SUPPLY VOLTAGE (V)
OFFSET FREQUENCY (Hz)
PHASE NOISE vs. OFFSET FREQUENCY
MAX7032 toc35
REFERENCE SPUR MAGNITUDE vs. SUPPLY VOLTAGE
REFERENCE SPUR MAGNITUDE (dBc)
MAX7032 toc36
-40 -50 -60 PHASE NOISE (dBc/Hz) -70 -80 -90 -100 -110 -120 -130 -140 100 1k 10k 100k 1M fRF = 434MHz
-40 -45 -50 -55 -60 -65 -70 315MHz 433.92MHz
10M
2.1
2.4
2.7
3.0
3.3
3.6
OFFSET FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
FREQUENCY STABILITY vs. SUPPLY VOLTAGE
MAX7032 toc37
CLKOUT SPUR MAGNITUDE vs. SUPPLY VOLTAGE
fRF = 434MHz CLKOUT SPUR = fRF fCLKOUT 10pF LOAD CAPACITANCE fCLKOUT = fXTAL / 8 -60
MAX7032 toc38
10 8 FREQUENCY STABILITY (ppm) 6 4 2 0 -2 -4 -6 -8 -10 2.1 2.4 2.7 3.0 3.3 fRF = 434MHz fRF = 315MHz
-56 CLKOUT SPUR MAGNITUDE (dBc)
-58
-62 fCLKOUT = fXTAL / 2 -64 fCLKOUT = fXTAL / 4
-66 3.6 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
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11
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Pin Description
PIN 1 NAME PAVDD FUNCTION Power-Amplifier Supply Voltage. Bypass to GND with 0.01F and 220pF capacitors placed as close to the pin as possible. Envelope-Shaping Output. ROUT controls the power-amplifier envelope's rise and fall times. Connect ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as close to the inductor as possible with 680pF and 220pF capacitors as shown in the Typical Application Circuit. Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect TX/RX1 from TX/RX2. Functionally identical to TX/RX2. Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit. Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope shaping is desired), which may be part of the output-matching network to an antenna. Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation. Bypass AVDD to GND with 0.1F and 220pF capacitors placed as close to the pin as possible. Low-Noise Amplifier Input. Must be AC-coupled. Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set the LNA input impedance. Low-Noise Amplifier Output. Must be tied to AVDD through a parallel LC tank filter. AC-couple to MIXIN+. Noninverting Mixer Input. Must be AC-coupled to the LNA output. Inverting Mixer Input. Bypass to AVDD with a capacitor as close to LNA LC tank filter as possible. 330 Mixer Output. Connect to the input of the 10.7MHz filter. Inverting 330 IF Limiter Amplifier Input. Bypass to GND with a capacitor. Noninverting 330 IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter. Minimum-Level Peak Detector for Demodulator Output Maximum-Level Peak Detector for Demodulator Output Inverting Data Slicer Input Noninverting Data Slicer Input Noninverting Op Amp Input for the Sallen-Key Data Filter Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. Buffered Received-Signal-Strength Indicator Output Transmit/ Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to put the device in receive mode. It is internally pulled down. This function is also controlled by a configuration register. Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into shutdown mode. Receiver Data Output/Transmitter Data Input Divided Crystal Clock Buffered Output Digital Power-Supply Voltage. Bypass to GND with 0.01F and 220pF capacitors placed as close to the pin as possible.
2
ROUT
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
TX/RX1 TX/RX2 PAOUT AVDD LNAIN LNASRC LNAOUT MIXIN+ MIXINMIXOUT IFINIFIN+ PDMIN PDMAX DSDS+ OP+ DF RSSI T/R
23 24 25 26
ENABLE DATA CLKOUT DVDD
12
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Pin Description (continued)
PIN 27 28 29 30 31 32 -- NAME HVIN CS DIO SCLK XTAL1 XTAL2 EP FUNCTION High-Voltage Supply Input. For 3V operation, connect HVIN to PAVDD, AVDD, and DVDD. For 5V operation, tie only HVIN to 5V. Bypass HVIN to GND with 0.01F and 220pF capacitors placed as close to the pin as possible. Serial Interface Active-Low Chip Select Serial Interface Serial Data Input/Output Serial Interface Clock Input Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference. Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference. Exposed Pad. Solder evenly to the board's ground plane for proper operation.
MAX7032
Detailed Description
The MAX7032 300MHz to 450MHz CMOS transceiver and a few external components provide a complete transmit and receive chain from the antenna to the digital data interface. This device is designed for transmitting and receiving ASK and FSK data. All transmit frequencies are generated by a fractional-N-based synthesizer, allowing for very fine frequency steps in increments of fXTAL / 4096. The receive LO is generated by a traditional integer-N-based synthesizer. Depending on component selection, data rates as high as 33kbps (Manchester encoded) or 66kbps (NRZ encoded) can be achieved.
f=
1 2 L TOTAL x CTOTAL
Receiver
Low-Noise Amplifier (LNA) The LNA is a cascode amplifier with off-chip inductive degeneration that achieves approximately 30dB of voltage gain that is dependent on both the antenna matching network at the LNA input, and the LC tank network between the LNA output and the mixer inputs. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible match for low-input impedance such as a PC board trace antenna. A nominal value for this inductor with a 50 input impedance is 12nH at 315MHz and 10nH at 434MHz, but the inductance is affected by PC board trace length. LNASRC can be shorted to ground to increase sensitivity by approximately 1dB, but the input match must then be reoptimized. The LC tank filter connected to LNAOUT consists of L5 and C9 (see the Typical Application Circuit). Select L5 and C9 to resonate at the desired RF input frequency. The resonant frequency is given by:
where LTOTAL = L5 + LPARASITICS and CTOTAL = C9 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PC board traces, package pins, mixer input impedance, LNA output impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center frequency. Lab experimentation must be done to optimize the center frequency of the tank. The total parasitic capacitance is generally between 5pF and 7pF. Automatic Gain Control (AGC) When the AGC is enabled, it monitors the RSSI output. When the RSSI output reaches 1.28V, which corresponds to an RF input level of approximately -55dBm, the AGC switches on the LNA gain-reduction attenuator. The attenuator reduces the LNA gain by 36dB, thereby reducing the RSSI output by about 540mV to 740mV. The LNA resumes high-gain mode when the RSSI output level drops back below 680mV (approximately -59dBm at the RF input) for a programmable interval called the AGC dwell time. The AGC has a hysteresis of approximately 4dB. With the AGC function, the RSSI dynamic range is increased, allowing the MAX7032 to reliably produce an ASK output for RF input levels up to 0dBm with a modulation depth of 18dB. AGC is not required and can be disabled in either ASK or FSK mode. AGC is not necessary for FSK mode because large received signal levels do not affect FSK performance.
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13
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Mixer A unique feature of the MAX7032 is the integrated image rejection of the mixer. This eliminates the need for a costly front-end SAW filter for many applications. The advantage of not using a SAW filter is increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double-balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz intermediate frequency (IF) with low-side injection (i.e., fLO = fRF - fIF). The image-rejection circuit then combines these signals to achieve a typical 46dB of image rejection over the full temperature range. Lowside injection is required as high-side injection is not possible due to the on-chip image rejection. The IF output is driven by a source follower, biased to create a driving impedance of 330 to interface with an off-chip 330 ceramic IF filter. The voltage-conversion gain driving a 330 load is approximately 20dB. Note that the MIXIN+ and MIXIN- inputs are functionally identical. Integer-N Phase-Locked Loop (PLL) The MAX7032 utilizes a fixed integer-N PLL to generate the receive LO. All PLL components, including the loop filter, VCO, charge pump, asynchronous 24x divider, and phase-frequency detector are integrated on-chip. The loop bandwidth is approximately 500kHz. The relationship between RF, IF, and reference frequencies is given by: fREF = (fRF - fIF) / 24 Intermediate Frequency (IF) The IF section presents a differential 330 load to provide matching for the off-chip ceramic filter. The internal six AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpass filter type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz. For ASK data, the RSSI circuit demodulates the IF to baseband by producing a DC output proportional to the log of the IF signal level with a slope of approximately 15mV/dB. For FSK, the limiter output is fed into a PLL to demodulate the IF. The FSK demodulation slope is approximately 2.0mV/kHz. FSK Demodulator The FSK demodulator uses an integrated 10.7MHz PLL that tracks the input RF modulation and converts the frequency deviation into a voltage difference. The PLL is illustrated in Figure 1. The input to the PLL comes from the output of the IF limiting amplifiers. The PLL control voltage responds to changes in the frequency of the input signal with a nominal gain of 2.0mV/kHz. For example, an FSK peak-to-peak deviation of 50kHz generates
14
TO FSK BASEBAND FILTER AND DATA SLICER PHASE DETECTOR IF LIMITING AMPS CHARGE PUMP LOOP FILTER 10.7MHz VCO 2.0mV/kHz
Figure 1. FSK Demodulator PLL Block Diagram
a 100mVP-P signal on the control line. This control voltage is then filtered and sliced by the baseband circuitry. The FSK demodulator PLL requires calibration to overcome variations in process, voltage, and temperature. For more information on calibrating the FSK demodulator, see the Calibration section. The maximum calibration time is 150s. In discontinuous receive (DRX) mode, the FSK demodulator calibration occurs automatically just after the IC exits sleep mode. Data Filter The data filter for the demodulated data is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency in kHz should be set to approximately 3 times the fastest expected Manchester data rate in kbps from the transmitter (1.5 times the fastest expected NRZ data rate) for ASK. For FSK, the corner frequency should be set to approximately 2 times the fastest expected Manchester data rate in kbps from the transmitter (1 times the fastest expected NRZ data rate). Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. Table 1 lists coefficients to calculate CF1 and CF2.
Table 1. Coefficients to Calculate CF1 and CF2
FILTER TYPE Butterworth (Q = 0.707) Bessel (Q = 0.577) a 1.414 1.3617 b 1.000 0.618
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
The configuration shown in Figure 2 can create a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of the capacitors, use the following equations, along with the coefficients in Table 1: b CF1 = a(100k)()(fC ) a CF2 = 4(100k)()(fC ) where fC is the desired 3dB corner frequency. For example, choose a Butterworth filter response with a corner frequency of 5kHz:
MAX7032
DS+
MAX7032
MAX7032
RSSI OR FSK DEMOD
100k
100k
OP+ CF2
DF CF1
Figure 2. Sallen-Key Lowpass Data Filter
1.000 CF1 = 450pF (1.414)(100k)(3.14)(5kHz) 1.414 CF2 = 225pF (4)(100k)(3.14)(5kHz) Choosing standard capacitor values changes CF1 to 470pF and CF2 to 220pF. In the Typical Application Circuit, CF1 and CF2 are named C16 and C17, respectively. Data Slicer The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. The threshold voltage is set by the voltage on the DS- pin, which is connected to the negative input of the data-slicer comparator. Numerous configurations can be used to generate the data-slicer threshold. For example, the circuit in Figure 3 shows a simple method using only one resistor and one capacitor. This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R and C affect how fast the threshold tracks the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower (about 10 times) than the lowest expected data rate. With this configuration, a long string of NRZ zeros or ones can cause the threshold to drift. This configuration works
DATA
DATA SLICER
DSR C
DS+
Figure 3. Generating Data Slicer Threshold Using a Lowpass Filter
best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. Figure 4 shows a configuration that uses the positive and negative peak detectors to generate the threshold. This configuration sets the threshold to the midpoint between a high output and a low output of the data filter. Peak Detectors The maximum peak detector (PDMAX) and minimum peak detector (PDMIN), with resistors and capacitors shown in Figure 4, create DC output voltages equal to the high and low peak values of the filtered ASK or FSK demodulated signals. The resistors provide a path for the capacitors to discharge, allowing the peak detectors to dynamically follow peak changes of the data filter output voltages.
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15
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
MAX7032
MAX7032
PDMIN
DATA SLICER PEAK DET PEAK DET
MINIMUM PEAK DETECTOR
BASEBAND FILTER
DATA PDMAX R C PDMIN R
TRK_EN = 1 MAXIMUM PEAK DETECTOR
TO SLICER INPUT
PDMAX
C
TRK_EN = 1
Figure 4. Generating Data Slicer Threshold Using the Peak Detectors Figure 5. Peak-Detector Track Enable
The maximum and minimum peak detectors can be used together to form a data slicer threshold voltage at a value midway between the maximum and minimum voltage levels of the data stream (see the Data Slicer section and Figure 4). The RC time constant of the peak-detector combining network should be set to at least 5 times the data period. If there is an event that causes a significant change in the magnitude of the baseband signal, such as an AGC gain switch or a power-up transient, the peak detectors may "catch" a false level. If a false peak is detected, the slicing level is incorrect. The MAX7032 has a feature called peak-detector track enable (TRK_EN), where the peak-detector outputs can be reset (see Figure 5). If TRK_EN is set (logic 1), both the maximum and minimum peak detectors follow the input signal. When TRK_EN is cleared (logic 0), the peak detectors revert to their normal operating mode. The TRK_EN function is automatically enabled for a short time whenever the IC is first powered up, or transitions from transmit to receive mode, or recovers from the sleep portion of DRX mode, or when an AGC gain switch occurs regardless of the bit setting. Since the peak detectors exhibit a fast-attack/slow-decay response, this feature allows for an extremely fast startup or AGC recovery. See Figure 6 for an illustration of a fast-recovery sequence. In addition to the automatic control of this function, the TRK_EN bits can be controlled through the serial interface (see the Serial Control Interface section).
RECEIVER ENABLED, TRK_EN SET TRK_EN CLEARED MAX PEAK DETECTOR
200mV/div FILTER OUTPUT MIN PEAK DETECTOR DATA OUTPUT DATA OUTPUT 2V/div 100s/div
Figure 6. Fast Receiver Recovery in FSK Mode Utilizing Peak Detectors
Transmitter
Power Amplifier (PA) The PA of the MAX7032 is a high-efficiency, opendrain, switch-mode amplifier. The PA with proper
16
output-matching network can drive a wide range of antenna impedances, which includes a small-loop PC board trace and a 50 antenna. The output-matching network for a 50 antenna is shown in the Typical Application Circuit. The output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT (pin 5). The optimal impedance at PAOUT is 250. When the output-matching network is properly tuned, the PA transmits power with a high overall efficiency of up to 32%. The efficiency of the PA itself is more than 46%. The output power is set by an external resistor at
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
PAOUT, and is also dependent on the external antenna and antenna-matching network at the PA output. Envelope Shaping The MAX7032 features an internal envelope-shaping resistor, which connects between the open-drain output of the PA and the power supply (see Typical Application Circuit). The envelope-shaping resistor slows the turn-on/turn-off of the PA in ASK mode, and results in a smaller spectral width of the modulated PA output signal. Fractional-N PLL The MAX7032 utilizes a fully integrated fractional-N PLL for its transmit frequency synthesizer. All PLL components, including the loop filter, are included on chip. The loop bandwidth is approximately 200kHz. The 16bit fractional-N topology allows the transmit frequency to be adjusted in increments of fXTAL / 4096. The finefrequency-adjustment capability enables the use of a single crystal, as the transmit frequency can be set within 2kHz of the receive frequency. The fractional-N topology also allows exact FSK frequency deviations to be programmed, completely eliminating the problems associated with generating frequency deviations by crystal oscillator pulling. The integer and fractional portions of the PLL divider ratio set the transmit frequency. The example below shows how to calculate fXTAL and how to determine the correct values to be loaded to register TxLOW (register 0x0D and 0x0E) and TxHIGH (registers 0x0F and 0x10): Assume the receiver/ASK transmit frequency = 315MHz, and IF = 10.7MHz: (f - 10.7) fXTAL = RF = 12.67917MHz 24 and fRF = 24.8439 = transmit PLL divider ratio fXTAL Due to the nature of the transmit PLL frequency divider, a fixed offset of 16 must be subtracted from the transmit PLL divider ratio for programming the MAX7032's transmit frequency registers. To determine the value to program the MAX7032's transmit frequency registers, convert the decimal value of the following equation to the nearest hexadecimal value:
MAX7032
fRF - 16 x 4096 = decimal value to program f XTAL transmit frequency registers In this example, the rounded decimal value is 36,225, or 8D81 hexadecimal. The upper byte (8D) is loaded into register 0x0D, and the low byte (81) is loaded into register 0x0E. In FSK mode, the transmit frequencies equal the upper and lower frequencies that are programmed into the MAX7032's transmit frequency registers. Calculate the upper frequency in the same way as shown above. In ASK mode, the transmit frequency equals the lower frequency that is programmed into the MAX7032's transmit frequency registers.
Power-Supply Connections
The MAX7032 can be powered from a 2.1V to 3.6V supply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is used, then the on-chip linear regulator reduces the 5V supply to the 3V needed to operate the chip. To operate the MAX7032 from a 3V supply, connect PAVDD, AVDD, DVDD, and HVIN to the 3V supply. When using a 5V supply, connect the supply to HVIN only and connect AVDD, PAVDD, and DVDD together. In both cases, bypass DVDD, PAVDD and HVIN to GND with a 0.01F and 220pF capacitor and bypass AVDD to GND with a 0.1F and 220pF capacitor. Bypass T/R, ENABLE, DATA, CS, DIO, and SCLK with 10pF capacitors to GND. Place all bypass capacitors as close to the respective pins as possible.
Transmit/Receive Antenna Switch
The MAX7032 features an internal SPST RF switch, which, when combined with a few external components, allows the transmit and receive pins to share a common antenna (see the Typical Application Circuit). In receive mode, the switch is open and the power amplifier is shut down, presenting a high impedance to minimize the loading of the LNA. In transmit mode, the switch closes to complete a resonant tank circuit at the PA output and forms an RF short at the input to the LNA. In this mode, the external passive components couple the output of the PA to the antenna to protect the LNA input from strong transmitted signals. The switch state is controlled either by an external digital input or by the T/R bit, which is bit 6 in the configuration 0 register, T/R. Drive the T/R pin high to put the device in transmit mode; drive the T/R pin low to put the device in receive mode.
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17
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Crystal Oscillator (XTAL)
The XTAL oscillator in the MAX7032 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2 pins. In most cases, this corresponds to a 4.5pF load capacitance applied to the external crystal when typical PC board parasitics are added. It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7032 crystal oscillator plus PC board parasitics. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. In actuality, the oscillator pulls every crystal. The crystal's natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: C 1 1 fP = m - x 106 2 CCASE + CLOAD CCASE + CSPEC where: fp is the amount the crystal frequency is pulled in ppm. Cm is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. When the crystal is loaded as specified, i.e., CLOAD = CSPEC, the frequency pulling equals zero.
Serial Control Interface
Communication Protocol The MAX7032 programs through a 3-wire interface. The data input must follow the timing diagrams shown in Figures 7, 8, and 9. Note that the DIO line must be held LOW while CS is high. This is to prevent the MAX7032 from entering discontinuous receive mode if the DRX bit is high. The data is latched on the rising edge of SCLK, and therefore must be stable before that edge. The data sequencing is MSB first, the command (C[1:0] see Table 2), the register address (A[5:0] see Table 3), and the data (D[7:0] see Table 4).
Table 2. Command Bits
C[1:0] 0x0 0x1 0x2 0x3 DESCRIPTION No operation Write data Read data Master reset
tCS CS tCSS tSC SCLK tDH tDS DIO HI-Z tTH HI-Z tDV D7 tDO D0 tTR HI-Z tCL tCH tCSH
DATA IN
DATA OUT
Figure 7. Serial Interface Timing Diagram 18 ______________________________________________________________________________________
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Table 3. Register Summary
REGISTER A[5:0] 0x00 REGISTER NAME Power configuration DESCRIPTION Enables/disables the LNA, AGC, mixer, baseband, peak detectors, PA, and RSSI output (see Table 5). Controls AGC lock, gain state, peak-detector tracking, polling timer and FSK calibration, clock signal output, and sleep mode (see Table 6). Sets options for modulation, TX/RX mode, manual-gain mode, discontinuous receive mode, off-timer and on-timer prescalers (see Table 7). Sets options for automatic FSK calibration, clock output, output clock divider ratio, AGC dwell timer (see Tables 8, 10, 11, and 12). Sets the internal clock frequency divisor. This register must be set to the integer result of fXTAL / 100kHz (see the Oscillator Frequency Register section). Sets the duration that the MAX7032 remains in low-power mode when DRX is active (see Table 12). Increases maximum time the MAX7032 stays in lower power mode while CPU wakes up when DRX is active (see Table 13). During the time set by the RF settling timer, the MAX7032 is powered on with the peak detectors and the data outputs disabled to allow time for the RF section to settle. DIO must be driven low at any time during tLOW = tCPU + tRF + tON or the timer sequence restarts (see Table 14). Sets the duration that the MAX7032 remains in active mode when DRX is active (see Table 15).
MAX7032
0x01
Control
0x02
Configuration0
0x03
Configuration1
0x05 0x06 0x07 0x08 0x09
Oscillator frequency Off timer--tOFF (upper byte) Off timer--tOFF (lower byte) CPU recovery timer--tCPU RF settling timer--tRF (upper byte) RF settling timer--tRF (lower byte) On timer--tON (upper byte) On timer--tON (lower byte) Transmitter low-frequency setting--TxLOW (upper byte) Transmitter low-frequency setting--TxLOW (lower byte) Transmitter high-frequency setting--TxHIGH (upper byte) Transmitter high-frequency setting--TxHIGH (lower byte) Status register (read only)
0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x1A
Sets the low frequency (FSK) of the transmitter or the carrier frequency of ASK for the fractional-N synthesizer.
Sets the high frequency (FSK) of the transmitter for the fractional-N synthesizer.
Provides status for PLL lock, AGC state, crystal operation, polling timer, and FSK calibration (see Table 9).
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19
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
CS
SCLK
DIO
C1
C0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND
ADDRESS
DATA
Figure 8. Data Input Diagram
CS SCLK DIO 0 0 0 0 DATA 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 R7 R0
1
0
A5
A4
A3
A2
A1
A0
READ COMMAND
ADDRESS
REGISTER DATA 16 BITS OF DATA
REGISTER DATA
CS SCLK DIO 1 0 A5 A4 A3 A2 A1 A0 0 0 0 0 DATA 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 A3
READ COMMAND
ADDRESS
REGISTER DATA 8 BITS OF DATA
Figure 9. Read Command on a 3-Wire Serial Interface
DIO is selected as an output of the MAX7032 for the following CS cycle whenever a READ command is received. The CPU must tri-state the DIO line on the cycle of CS that follows a read command, so the MAX7032 can drive the data output line. Figure 9 shows the diagram of the 3-wire interface. Note that the user can choose to send either 16 cycles of SLCK or just eight cycles as all the registers are 8-bits wide. The
user must drive DIO low at the end of the read sequence. The MASTER RESET command (0x3) (see Table 2) sends a reset signal to all the internal registers of the MAX7032 just like a power-off and power-on sequence would do. The reset signal remains active for as long as CS is high after the command is sent.
20
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Table 4. Register Configuration
NAME (ADDRESS) POWER[7:0] (0x00) CONTRL[7:0] (0x01) CONF0[7:0] (0x02) CONF1[7:0] (0x03) OSC[7:0] (0x05) tOFF[15:8] (0x06) tOFF [7:0] (0x07) tCPU[7:0] (0x08) tRF[15:8] (0x09) tRF [7:0] (0x0A) tON[15:8] (0x0B) tON [7:0] (0x0C) TxLOW[15:8] (0x0D) TxLOW[7:0] (0x0E) TxHIGH[15:8] (0x0F) TxHIGH[7:0] (0x10) STATUS[7:0] (0x1A) DATA D7 LNA AGCLK Mode -- OSC7 tOFF 15 tOFF 7 tCPU 7 tRF 15 tRF 7 tON 15 tON 7 TxL15 TxL7 TxH15 TxH7 LCKD D6 AGC GAIN T/R ACAL OSC6 tOFF 14 tOFF 6 tCPU 6 tRF 14 tRF 6 tON 14 tON 6 TxL14 TxL6 TxH14 TxH6 GAINS D5 MIXER TRK_EN MGAIN CLKOF OSC5 tOFF 13 tOFF 5 tCPU 5 tRF 13 tRF 5 tON 13 tON 5 TxL13 TxL5 TxH13 TxH5 CLKON DRX CDIV1 OSC4 tOFF 12 tOFF 4 tCPU 4 tRF 12 tRF 4 tON 12 tON 4 TxL12 TxL4 TxH12 TxH4 0 D4 BaseB -- D3 PkDet PCAL OFPS1 CDIV0 OSC3 tOFF 11 tOFF 3 tCPU 3 tRF 11 tRF 3 tON 11 tON 3 TxL11 TxL3 TxH11 TxH3 0 PA FCAL OFPS0 DT2 OSC2 tOFF 10 tOFF 2 tCPU 2 tRF 10 tRF 2 tON 10 tON 2 TxL10 TxL2 TxH10 TxH2 0 D2 D1 RSSIO CKOUT ONPS1 DT1 OSC1 tOFF 9 tOFF 1 tCPU 1 tRF 9 tRF 1 tON 9 tON 1 TxL9 TxL1 TxH9 TxH1 PCALD X SLEEP ONPS0 DT0 OSC0 tOFF 8 tOFF 0 tCPU 0 tRF 8 tRF 0 tON 8 tON 0 TxL8 TxL0 TxH8 TxH0 FCALD D0
MAX7032
Continuous Receive Mode (DRX = 0) In continuous receive mode, individual analog modules can be powered on directly through the power configuration register (register 0x00). The SLEEP bit (bit 0 in register 0x01) overrides the power configuration registers and puts the device into deep-sleep mode when set. It is also necessary to write the frequency divisor of the external crystal in the oscillator frequency register (register 0x05) to optimize image rejection and to enable accurate calibration sequences for the polling timer and the FSK demodulator. This number is the integer result of fXTAL / 100kHz. If the FSK receive function is selected, it is necessary to perform an FSK calibration to allow operation; otherwise, the demodulator is saturated. Polling timer calibration is not necessary. See the Calibration section for more information. Discontinuous Receive Mode (DRX = 1) In the discontinuous receive mode (DRX = 1), the receiver modules set to logic 1 by the power register (0x00) of the MAX7032 toggle between OFF and ON, according to internal timers tOFF, tCPU, tRF, and tON. It
is also necessary to write the frequency divisor of the external crystal in the oscillator frequency register (register 0x05). This number is the integer result of fXTAL / 100kHz. Before entering the discontinuous receive mode for the first time, it is also necessary to calibrate the timers (see the Calibration section). The MAX7032 uses a series of internal timers (tOFF, tCPU, tRF, and tON) to control its power-up sequence. The timer sequence begins when both CS and DIO are one. The MAX7032 has an internal pullup on the DIO pin, so the user must tri-state the DIO line when CS goes high. The external CPU can then go to a sleep mode during tOFF. A high-to-low transition on DIO, or a low level on DIO serves as the wake-up signal for the CPU, which must then start its wake-up procedure, and drive DIO low before tLOW expires (tCPU + tRF + tON). Once tRF expires and tON is active, the MAX7032 enables the data output. The CPU must then keep DIO low for as long as it may need to analyze any received data. Releasing DIO after tON expires causes the MAX7032 to pull up DIO, reinitiating the tOFF timer.
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21
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Table 5. Power-Configuration Register (Address: 0x00)
BIT ID LNA AGC MIXER BaseB PkDet PA RSSIO X BIT NAME LNA enable AGC enable Mixer enable Baseband enable Peak-detector enable Transmitter PA enable RSSI amplifier enable None BIT LOCATION (0 = LSB) 7 6 5 4 3 2 1 0 FUNCTION 1 = Enable LNA 0 = Disable LNA 1 = Enable AGC 0 = Disable AGC 1 = Enable mixer 0 = Disable mixer 1 = Enable baseband 0 = Disable baseband 1 = Enable peak detector 0 = Disable peak detector 1 = Enable PA 0 = Disable PA 1 = Enable buffer 0 = Disable buffer Not used
Table 6. Control Register (Address: 0x01)
BIT ID AGCLK GAIN TRK_EN X PCAL FCAL CKOUT BIT NAME AGC locking feature Gain state Manual peak-detector tracking None Polling timer calibration FSK calibration Crystal clock output enable BIT LOCATION (0 = LSB) 7 6 5 4 3 2 1 1 = Enable AGC lock 0 = Disable AGC lock 1 = Force manual high-gain state if MGAIN = 1 0 = Force manual low-gain state if MGAIN = 1 1 = Force manual peak-detector tracking 0 = Release peak-detector tracking Not used 1 = Perform polling timer calibration Automatically reset to zero once calibration is completed 1 = Perform FSK calibration Automatically reset to zero once calibration is completed 1 = Enable crystal clock output 0 = Disable crystal clock output 1 = Deep-sleep mode, regardless the state of ENABLE pin 0 = Normal operation FUNCTION
SLEEP
Sleep mode
0
22
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Table 7. Configuration 0 Register (Address: 0x02)
BIT ID BIT NAME BIT LOCATION (0 = LSB) FUNCTION 1 = Enable FSK for both receive and transmit 0 = Enable ASK for both receive and transmit 1 = Enable transmit mode of the transceiver, regardless the state of pin T/R 0 = Enable receive mode of the transceiver when pin T/R = 0 1 = Enable manual-gain mode 0 = Disable manual-gain mode 1 = Enable DRX 0 = Disable DRX Sets the time base for the off timer (see the Off Timer section) Sets the time base for the on timer (see the On Timer section)
MAX7032
MODE
FSK or ASK modulation
7
T/R
Transmit or receive
6
MGAIN DRX OFPS1 OFPS0 ONPS1 ONPS0
Manual gain mode Discontinuous receive mode Off-timer prescaler Off-timer prescaler On-timer prescaler On-timer prescaler
5 4 3 2 1 0
Table 8. Configuration 1 Register (Address: 0x03)
BIT ID X ACAL None Automatic FSK calibration BIT NAME BIT LOCATION (0 = LSB) 7 6 Not used 1 = Enable automatic FSK calibration approximately once every 60s 0 = Disable automatic FSK calibration 1 = Enable continuous clock output when CKOUT =1 0 = Continuous clock output; if CKOUT = 1, clock output is active during TON (DRX mode) or when EN pin is high (continuous receive mode) CLKOUT crystal-divider MSB CLKOUT crystal-divider LSB AGC dwell timer MSB AGC dwell timer AGC dwell timer LSB FUNCTION
CLKOF
Continuous clock output (even during tOFF or when EN pin is low)
5
CDIV1 CDIV0 DT2 DT1 DT0
Crystal divider Crystal divider AGC dwell timer AGC dwell timer AGC dwell timer
4 3 2 1 0
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23
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Table 9. Status Register (Read Only) (Address: 0x1A)
BIT ID BIT NAME BIT LOCATION (0 = LSB) 7 FUNCTION 1 = Internal PLL is locked 0 = Internal PLL is not locked so the MAX7032 does not receive or transmit data 1 = LNA in high-gain state 0 = LNA in low-gain state 1 = Valid clock at crystal inputs 0 = No valid clock signal seen at the crystal inputs Zero Zero Zero 1 = Polling timer calibration is completed 0 = Polling timer calibration is in progress or not completed 1 = FSK calibration is completed 0 = FSK calibration is in progress or not completed
LCKD
Lock detect
GAINS
AGC gain state
6
CLKON X X X PCALD
Clock/crystal alive None None None Polling timer calibration done
5 4 3 2 1
FCALD
FSK calibration done
0
Table 10. Clock Output Divider Ratio Configuration
CKOUT 0 1 1 1 1 CDIV1 X 0 0 1 1 CDIV0 X 0 1 0 1 CLOCKOUT FREQUENCY Disabled at logic 0 fXTAL fXTAL / 2 fXTAL / 4 fXTAL / 8
hexadecimal value written to the oscillator frequency register is the nearest integer result of fXTAL / 100kHz. For example, if data is being received at 315MHz, the crystal frequency is 12.67917MHz. Dividing the crystal frequency by 100kHz and rounding to the nearest integer gives 127, or 0x7F hex. So for 315MHz, 0x7F would be written to the oscillator frequency register. AGC Dwell Timer (Address 0x03) The AGC dwell timer holds the AGC in low-gain state for a set amount of time after the power level drops below the AGC switching threshold. After that set amount of time, if the power level is still below the AGC threshold, the LNA goes into high-gain state. This is important for ASK since the modulated data may have a high level above the threshold and a low level below the threshold, which without the dwell timer would cause the AGC to switch on every bit.
Oscillator Frequency Register (Address 0x05) The MAX7032 has an internal frequency divider that divides down the crystal frequency to 100kHz. The MAX7032 uses the 100kHz clock signal when calibrating itself and also to set image-rejection frequency. The
24
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
The AGC dwell time is dependent on the crystal frequency and the bit settings of the AGC dwell timer. To calculate the dwell time, use the following equation: Dwell Time = 2K fXTAL Calibration The MAX7032 must be calibrated to ensure accurate timing of the off timer in discontinuous receive mode or when receiving FSK signals. The first step in calibration is ensuring that the oscillator frequency register (register: 0x05) has been programmed with the correct divisor value (see the Oscillator Frequency Register section). Next, enable the mixer to turn the crystal driver on. Calibrate the polling timer by setting PCAL = 1 in the control register (register 0x01, bit 3). Upon completion, the PCALD bit in the status register (register 0x1A, bit 1) is 1, and the PCAL bit is reset to zero. If using the MAX7032 in continuous receive mode, polling timer calibration is not needed. To calibrate the FSK receiver, set FCAL = 1. Upon completion, the FCALD bit in the status register (register 0x08) is one, and the FCAL bit is reset to zero. When in continuous receive mode and receiving FSK data, recalibrate the FSK receiver after a significant change in temperature or supply voltage. An autocal feature is provided that performs a calibration every minute (ACAL bit, Table 8). When in discontinuous receive mode, the polling timer and FSK receiver (if enabled) are automatically calibrated every wake-up cycle. Off Timer (tOFF) The off timer, tOFF (see Figure 10), is a 16-bit timer that is configured using register 0x06 for the upper byte, register 0x07 for the lower byte, and bits OFPS1 and OFPS0 in the configuration 0 register (register 0x02, bit 3 and bit 2, respectively). Table 12 summarizes the configuration of the tOFF timer. The OFPS1 and OFPS0 bits set the size of the shortest time possible (tOFF time base). The data written to the tOFF registers (register 0x06 and register 0x07) are multiplied by the time base to give the total tOFF time. See the example below. On power-up, the off-timer registers are reset to zero and must be written before using DRX mode.
MAX7032
where K is an odd integer in decimal from 9 to 23; see Table 11. To calculate the value of K, use the following equation and use the next odd integer higher than the calculated result: K 3.3 x log10 (Dwell Time x fXTAL) For Manchester Code (50% duty cycle), set the dwell time to at least twice the bit period. For NRZ data, set the dwell to greater than the period of the longest string of zeros or ones. For example, using Manchester Code at 315MHz (fXTAL = 12.679MHz) with a data rate of 4kbps (bit period = 125s), the dwell time needs to be greater than 250s: K 3.3 x log10 (250s x 12.679MHz) 11.553 Choose the register value to be the next odd integer value higher than 11.553, which is K = 13. The default value of the AGC dwell timer on power-up or rest is zero (K = 9).
Table 11. AGC Dwell Timer Configuration (Address 0x03)
DT2 0 0 0 0 1 1 1 1 DT1 0 0 1 1 0 0 1 1 DT0 0 1 0 1 0 1 0 1 DESCRIPTION K=9 K = 11 K = 13 K = 15 K = 17 K = 19 K = 21 K = 23
Table 12. Off-Timer (tOFF) Configuration
OFPS1 0 0 1 1 OFPS0 0 1 0 1 tOFF TIME BASE 120s 480s 1920s 7680s MIN tOFF REG 0x06 = 0x00; REG 0x07 = 0x01 120s 480s 1.92ms 7.68ms MAX tOFF REG 0x06 = 0xFF; REG 0x07 = 0xFF 7.86s 31.46s 2 min 6s 8 min 23s
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25
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
CS DIO tOFF tCPU tOFF tCPU tLOW tRF tON ASK_DATA OR FSK_DATA tRF tON
Figure 10. DRX Mode Sequence of the MAX7032
Set OFPS1 to be 1 and OFPS0 to be 1. That sets the tOFF time base (1 LSB) to be 7680s. Set REG 0x06 and REG 0x07 to be FFFF, which is 65535 in decimal. Therefore, the total tOFF is: tOFF = 7680s x 65535 = 8min 23s During tOFF, the MAX7032 is operating with very low supply current (23.4A typ), where all its modules are turned off, except for the tOFF timer itself. Upon completion of the tOFF time, the MAX7032 signals the user by asserting DIO low. CPU Recovery Timer (tCPU) The CPU recovery timer, tCPU (see Figure 10) is used to delay power up of the MAX7032, thereby providing extra power savings and giving the CPU time to complete its own power-on sequence. The CPU is signaled to begin powering up when the DIO line is pulled low by the MAX7032 at the end of tOFF. Then, tCPU begins counting, while DIO is held low by the MAX7032. At the end of tCPU, the tRF counter begins. tCPU is an 8-bit timer, configured through register 0x08. The possible tCPU settings are summarized in Table 13. The data written to the tCPU register (register 0x08) is multiplied by 120s to give the total tCPU time. See the example below. On power-up, the CPU timer register is reset to zero and must be written before using DRX mode. Set REG 0x08 to be FF in hex, which is 255 in decimal. Therefore, the total tCPU is: tCPU = 120s x 255 = 30.6ms
RF Settling Timer (tRF) The RF settling timer, tRF (see Figure 10), allows the RF sections of the MAX7032 to power up and stabilize before ASK or FSK data is received. tRF begins counting once tCPU has expired. At the beginning of tRF, the modules selected in the power control register (register 0x00) are all powered up and the peak detectors are in the track mode and have the tRF period to settle. tRF is a 16-bit timer, configured through register 0x09 (upper byte) and register 0x0A (lower byte). The possible tRF settings are listed in Table 14. The data written to the tRF register (register 0x09 and register 0x0A) are multiplied by 120s to give the total tRF time. See the example in the CPU Recovery Time (tCPU) section. On power-up, the RF timer registers are reset to zero and must be written before using DRX mode.
Table 13. CPU Recovery Timer (tCPU) Configuration
TIME BASE (s) 120 MIN tCPU REG 0x08 = 0x01 (s) 120 MAX tCPU REG 0x08 = 0xFF (ms) 30.6
Table 14. RF Settling Timer (tRF) Configuration
tRF TIME BASE (s) 120 MIN tRF REG 0x09 = 0x00 REG 0x0A = 0x01 (s) 120 MAX tRF REG 0x09 = 0xFF REG 0x0A = 0xFF (s) 7.86
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Table 15. On-Timer (tON) Configuration
ONPS1 0 0 1 1 ONPS0 0 1 0 1 tON TIME BASE 120s 480s 1920s 7680s MIN tON REG 0x0B = 0x00 REG 0x0C = 0x01 120s 480s 1.92s 7.68s MAX tON REG 0x0B = 0xFF REG 0x0C = 0xFF 7.86s 31.46s 2 min 6s 8 min 23s
MAX7032
On Timer (tON) The on timer, tON (see Figure 10), is a 16-bit timer that is configured through register 0x0B for the upper byte, register 0x0C for the lower byte (Table 15). The information stored in this timer provides an additional way to control the duration of the on time of the receiver. The CPU must begin driving DIO low any time during tLOW = tCPU + tRF + tON. If the CPU fails to drive DIO low at the end of tON, DIO is pulled high through the internal pullup resistor, and the time sequence is restarted, leaving the MAX7032 powered down. Any time the DIO line is driven high while the DRX = 1, the DRX sequence is initiated, as defined in Figure 10. In the event that the CPU is processing data, after tON expires, the CPU should keep the MAX7032 awake by holding the DIO line low. The data written to the tON register (register 0x0B and register 0x0C) are multiplied by the t ON time base (Table 15) to give the total tON time. See the example in the Off Timer (tOFF) section. On power-up, the on-timer register is reset to zero and must be written before using DRX mode. Transmitter Low-Frequency Register (TxLOW) The TxLOW register sets the divider information of the fractional-N synthesizer for the lower transmit frequency in FSK mode. See the example given in the Fractional-N PLL section. In ASK mode, TxLOW determines the carrier frequency. Transmitter High-Frequency Register (TxHIGH) The TxHIGH register sets the divider information of the fractional-N synthesizer for the upper transmit frequency in the FSK mode. In ASK mode, the content of TxHIGH is not used. The 16-bit register contains the binary representation of the Tx PLL divider ratio, which is shown in the example in the Fractional-N PLL section.
Applications Information
Output Matching to 50
When matched to a 50 system, the MAX7032's PA is capable of delivering +10dBm of output power at VDD = +2.7V. The output of the PA is an open-drain transistor that requires external impedance matching and pullup inductance for proper biasing. The pullup inductance from the PA to PAVDD serves three main purposes: it resonates the capacitive PA output, provides biasing for the PA, and becomes a high-frequency choke to prevent RF energy from coupling into VDD. The network also forms a bandpass filter that provides attention for the higher order harmonics.
Output Matching to PC Board Loop Antenna
In most applications, the MAX7032 must be impedance matched to a small-loop antenna. The antenna is usually fabricated out of a copper trace on a PC board in a rectangular, circular, or square pattern. The antenna has an impedance that consists of a lossy component and a radiative component. To achieve high radiating efficiency, the radiative component should be as high as possible, while minimizing the lossy component. In addition, the loop antenna has an inherent loop inductance associated with it (assuming the antenna is terminated to ground). For example, in a typical application, the radiative impedance is less than 0.5, the lossy impedance is less than 0.7, and the inductance is approximately 50nH to 100nH.
Layout Considerations
A properly designed PC board is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of / 10 or longer act as antennas, where is the wavelength.
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27
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Keeping the traces short also reduces parasitic inductance. Generally, 1in of PC board trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting to a 100nH inductor adds an extra 10nH of inductance, or 10%. To reduce parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to the ground plane, and place decoupling capacitors as close to all VDD pins and HVIN as possible.
Typical Application Circuit
SCLK DIO VDD Y1 3.0V C23 VDD C18 C21 VDD 1 C24 C22 2 R3* T/R 3 C2 C1 L1 4 5 L2 C4 C3 C5 C7 C8 L3 C6 L6 DS+ 7 8 L4 LNAOUT MIXOUT LNAIN LNASRC MIXINPDMIN PDMAX MIXIN+ 18 VDD 6 AVDD EXPOSED PAD OP+ 19 C17 C16 TX/RX1 TX/RX2 ROUT PAVDD 32 XTAL2 31 XTAL1 C20 30 SCLK 29 DIO 28 CS 27 HVIN 26 DVDD 25 CLKOUT 24 C19 CLOCK OUTPUT CS
DATA
DATA
ENABLE
23
ENABLE TRANSMIT/ RECEIVE
22
MAX7032
RSSI
21
PAOUT
DF
20
IFIN-
IFIN+
DS-
17
9
10 C10 C9 L5
11 C12 VDD
12
13 C13
14
15
16
R1 C15
IN
GND Y2
OUT C14
R2
C11 *OPTIONAL POWER-ADJUST RESISTOR
28
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Table 16. Component Values for Typical Application Circuit
COMPONENT C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 L1 L2 L3 L4 L5 L6 R1 R2 R3 Y1 Y2 VALUE FOR 433.92MHz RF 220pF 680pF 6.8pF 6.8pF 10pF 220pF 0.1F 100pF 1.8pF 100pF 220pF 100pF 1500pF 0.047F 0.047F 470pF 220pF 220pF 0.01F 100pF 100pF 220pF 0.01F 0.01F 22nH 22nH 22nH 10nH 16nH 68nH 100k 100k 0 17.63416MHz 10.7MHz ceramic filter VALUE FOR 315MHz RF 220pF 680pF 12pF 10pF 22pF 220pF 0.1F 100pF 2.7pF 100pF 220pF 100pF 1500pF 0.047F 0.047F 470pF 220pF 220pF 0.01F 100pF 100pF 220pF 0.01F 0.01F 27nH 30nH 30nH 12nH 30nH 100nH 100k 100k 0 12.67917MHz 10.7MHz ceramic filter DESCRIPTION 10% 10% 5% 5% 5% 10% 10% 5% 0.1pF 5% 10% 5% 10% 10% 10% 10% 10% 10% 10% 5% 5% 10% 10% 10% Coilcraft 0603CS Coilcraft 0603CS Coilcraft 0603CS Coilcraft 0603CS Murata LQW18A Coilcraft 0603CS 5% 5% -- Crystal, 4.5pF load capacitance Murata SFECV10.7 series
Note: Component values vary depending on PC board layout.
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29
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Functional Diagram
LNAOUT MIXIN+ MIXIN9 10 11
MIXOUT 12
IFIN+ 14
IFIN13
0 LNAIN 7 LNA
IF LIMITING AMPS
LNASRC 8 90 I Q RX FREQUENCY DIVIDER XTAL1 31 CRYSTAL OSCILLATOR XTAL2 32 CHARGE PUMP PHASE DETECTOR TX FREQUENCY DIVIDER RSSI ASK
FSK DEMODULATOR
FSK 20 DF
100k RX VCO
100k 19 OP+ 21 RSSI
DATA FILTER
18 DS+
15 PDMIN
CLKOUT 25
1/K
16 PDMAX TX VCO MODULATOR RX DATA
HVIN 27
3.0V REGULATOR
LOOP FILTER
17 DS-
AVDD
6 EXPOSED PAD
MAX7032
PA
SERIAL INTERFACE AND DIGITAL LOGIC
30 SCLK 28 CS 29 DIO 24 DATA
2 ROUT
1 PAVDD
5 PAOUT
3 TX/RX1
4 TX/RX2
22 T/R
26 DVDD
23 ENABLE
30
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Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL
Pin Configuration
PROCESS: CMOS
DATA RSSI
Chip Information
MAX7032
TOP VIEW
ENABLE
OP+
DS+
24
CLKOUT DVDD HVIN CS DIO SCLK XTAL1 XTAL2
23
22
21
20
19
18
17 16 15 14 13
PDMAX PDMIN IFIN+ IFINMIXOUT MIXINMIXIN+ LNAOUT
DS-
T/R
DF
25 26 27 28 29 30 31 32 1
PAVDD
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 32 Thin QFN-EP PACKAGE CODE T3255-3 DOCUMENT NO. 21-0140
MAX7032
12 11 10 9
2
ROUT
3
TX/RX1
4
TX/RX2
5
PAOUT
6
AVDD
7
LNAIN
8
LNASRC
THIN QFN
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31
Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL MAX7032
Revision History
REVISION NUMBER 0 1 REVISION DATE 5/05 6/09 Initial release Made correction in Power Amplifier (PA) section DESCRIPTION PAGES CHANGED -- 16
MAX7032 MAX7032 MAX7032
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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